Keywords
RISC-V, BareMetal, device drivers

Technologies
RISC-V, C, riscv-gnu-toolchain, Python

RISC-V is an open-standard, royalty-free ISA whose modular design enables custom, domain-specific implementations. While this flexibility is a key strength of the RISC-V ecosystem, it has resulted in most open-source drivers and testing frameworks being tightly coupled to specific implementations, limiting portability and reuse. This project develops a bare-metal driver library and testing framework targeting core RISC-V components, including the CLINT, PLIC, CLIC, PMP, and core CSRs. Supporting both 32-bit and 64-bit architectures, register base addresses are resolved at compile time via a user-provided configuration file, enabling retargeting without modifying driver code. The targeted components configure local and external interrupts, define protected physical memory regions, and manage system trap handling and memory access control. A test API sits above the driver layer, decoupling hardware tests from implementation-specific details. By wrapping driver functions, tests can be written and reused across different RISC-V platforms without requiring detailed hardware knowledge.