RISC-V is a free open source instruction-set architecture (ISA. It offers complete customization through the addition of optional ex- tensions to the base ISA. However, open-source cores come with ma- jor verification challenges. These verification challenges can take up to 60% of the production cost. It is important that there are tools available to speed up the verification process. This project aims to develop a bare metal test framework for RISC-V processor to help verify the following. • Verify that a core implementation complies with the RISC-V ISA • Verify interrupt controls • Verify physical memory protection (PMP) & mode switching in hardware threads (HART) • Recognize the different extensions of RISC-V ISA • Verify functionality of peripherals • Deploy libraries in framework on a real device In RISC-V there are two types of interrupt controllers: Core Local Interrupt Controller (CLIC) and Platform Level Interrupt Controller (PLIC). Each interrupt source has a different priority and level. The framework needs to be able to access the necessary Control Status Registers (CSR) such as mstatus, mie, mcause, etc. These registers determine whether interrupts can occur, the types of interrupts al- lowed, the priority of each interrupt source, and the cause of the interrupt. The framework will provide a library of functions that can facilitate the configuration of both core local timer & software inter- rupts, as well as global platform interrupts typical caused by external I/Os. This will simplify the verification process of trap handlers. In RISC-V there is a a strict hierarchy of privilege levels that are used to protect components of the software stack from other compo- nent attempting to perform action their current privilege level does not permit them to. The processor tracks internally the current level of each HART, but there are CSRs manage privilege levels during control transitions when handling traps. The framework can access the required CSRs and trap instructions to manage and verify privi- lege level transitions for each HART. The framework should be able to configure the RISC-V processor to verify that the appropriate traps/exceptions are raised when attempts to violate privilege are identified. The framework will include support for configuring and testing a range of RISC-V peripherals. These peripherals will be accessible through dedicated functions and low-level register operations, allow- ing developers to verify correct behavior, measure performance, and simulate real-world usage scenarios. Specifically, the framework will support: • External Interrupts: Configuration and validation of interrupt sources with varying polarity (positive or negative) and triggering mechanisms (edge or level-sensitive). This includes testing interrupt prioritization and response latency. • GPIOs (General Purpose Input/Output): Read/write operations, pin di- rection control, and interrupt generation from GPIO events to ensure re- liable digital I/O handling. • Timers: Setup and verification of hardware timers for periodic interrupts, timekeeping, and delay generation. The framework will allow precise con- trol over timer registers and interrupt behavior. • Watchdog Timers: Configuration of watchdog timeout intervals and reset behavior to validate system recovery mechanisms under fault conditions. • MMU (Memory Management Unit): Testing of virtual memory transla- tion, access permissions, and page fault handling to ensure robust memory protection and address space isolation. • SAGE (Security Architecture for General-purpose Embedded systems): Integration and validation of SAGE-specific security features, including secure boot, cryptographic operations, and access control enforcement. • Debugging Interfaces: Monitoring of core status, halt/resume operations, and CSR access during debug mode. The framework will facilitate inter- action with the Debug Module to support breakpoint handling, single-step execution, and multi-hart control.

The base RISC-V ISA is quite minimal by design, it can be expanded by using optimal extensions that enable specialization for specific tasks.These extensions can add new instructions and change the for- mat of instructions as well. An example of this occurring is in the C extension, this extension is used to compress common 32-bit RISC-V instructions to a shorter 16-bits. This extension not only changes the binary format of the instructions it also changes how the instructions are written as shown above. The framework should be able to take RISC-V ISA instructions as input and then be able to verify if their output is the same as the excepted output.